Clocked-CMOS $(C^2MOS)$ is a logic family that combines static logic design with the synchronization achieved by using clock signals. In the early days of CMOS, many SSI and MSI chips were based on $C^2MOS$. In modern design, the technique is still useful in certain applications, such as dynamic “NORA” circuits.

Figure show the general structure of a $C^2MOS$ logic gate. The inputs A, B, and C are connected to complementary nFET/pFET pairs as in ordinary static design where they act like open or closed switches. The only modification is the insertion of two clocked FETs between the logic arrays and the output. Mp is controlled by $\bar \phi$ and separates the pFET logic block and $C_{out}$ while Mn is controlled by $\phi$ and serves the same function for the nFET logic block. The operation of the gate can be understood by studying the effects of the clock $\phi (t)$. When the clock is at a level of $\phi = 1$ as in Figure (a), both Mn and Mp are biased active. This connects both logic arrays to the output node, and the gate degenerates to its static equivalent circuit; the main difference are longer switching times due to the additional parasitics. After the transients have decayed, the output capacitor $C_{out}$ will be charged to a voltage $V_{out} = 0$ or $V_{out} = V_{DD}$. Figure (b) shows the circuit when $\phi = 0$ and both Mn and Mp are in cutoff. This isolates the output node from both logic arrays and the value of $V_{out} = V_{Result}$ is held on $C_{out}$. However, a moment's reflection will verify that this is identical to the problem of maintaining charge on a capacitive node using an OFF transmission gate, so that the value of $V_{out}$ will change in time. The result is only valid for the hold time $t_H$, which is an important characteristic of this type of circuit.

A basic inverter is shown in Figure. This is constructed by using a single complementary pair Mp1 and Mn1 in the usual manner. We have show the internal node capacitances $C_p$ and $C_n$ explicitly in the drawing. The operation of the clocked-CMOS inverter is summarized in figure below.

When ø = 1, both clocked FETs are active and the input controls the logic FETs Mp1 and Mn1. If $V_{in} = 0v$, then $V_{out} \rightarrow V_{DD}$, while an input of $V_{in} = V_{DD}$ results in $V_{out} \rightarrow 0v$; the general values are shown in Figure (a). Owing to the presence of $C_p$ and $C_n$, both $t_{LH}$ and $t_{HL}$ are larger than for a static inverter. For example, the charging time constant is given by

where $R_p$ and $R_{p1}$ are the pFET resistances. The output is driven into a Hi-Z state when the clock makes a transition to $\phi = 0$. As shown in Figure (b), the output voltage $V_{out} = V_X$ is maintained by charge storage on $C_{out}$.The voltages $V_p$ and $V_n$ across the capacitors $C_p$ and $C_n$ respectively, can be changed by the input, but the output remains isolated. The operation is identical to what can be achieved using a clocked transmission gate at the output of a static logic gate. Combing both aspects into a single gate allows the designer to automatically synchronize the data flow.

Cascading two oppositely-phased inverters results in the clocked latch shown in Figure. The timing is chosen to insure that when one inverter is accepting inputs, the other is in a Hi-Z hold state. The operation is similar to a master-slave DFF and is summarized in Figure.

A clock signal of $\phi = 1$ allows the first inverter to accept the input data voltage $V_D$ which results in a value of $V_{\bar D}$ on as shown in drawing (a) of Figure. This is true for both logic 0 and logic 1 inputs. When the clock changes to a value of $\phi = 0$, the first stage is driven into a Hi-Z state which the second stage accepts the value of $V_{\bar D}$ as an input. The voltage on $C_{out,2}$ then corresponds to the original value of $V_D$ this is illustrated in Figure(b). The output voltage can be maintained so long as the voltage $V_{\bar D}$ across $C_{out,1}$ remains within the appropriate voltage range, i.e.,

$0 \lt V_{\bar D}$ < $V_{IL}$

for a logic 0, and

$V_{IH}$ < $V_{\bar D}$ < $V_{DD}$

for a logic 1. Both $V_{IL}$ and $V_{IH}$ are determined by the VTC that is calculated when the circuit is operating like a static inverter. Charge leakage limits the minimum clock frequency $f_{min}$, while the charging and discharging delay times combine to specify the maximum clock frequency $f_{max}$.

Since $C^2MOS$ is based on static logic, it is a simple matter to design an entire family of gates with the same characteristics. Examples of these are the NAND2 gate in Figure (a) and the NOR2 gate in Figure (b). In principle, any AOI or OAI logic circuit may be created using the formalism. However, since the additional delay introduced by the clocking FETs cannot be eliminated, the logic family is automatically limited to slower systems.

A variation of $C^2MOS$ latch is shown in Figure . This uses a static inverter between two clocked circuits as the second stage to produce the output, which is not a tri-state node. This allows for the output to be taken at any time. The third stage circuit (which is the second $C^2MOS$ inverter in the chain) is now being used to provide clocked controlled feedback.

$C^2MOS$ logic provides a straightforward approach to synchronizing data flow while maintaining static logic ideas. Moreover, the Hi-Z characteristic of the output makes it useful for controlling signal races in the data path. As we shall see in the next chapter, the NORA (No Race) dynamic logic family employs $C^2MOS$ latches for just that purpose.