First, let us recall the operation of a full adder unit with the symbol shown in Figure.

The binary inputs are denoted by $a_n$ and $b_n$ and the carry-in bit is $c_n$. The outputs are the sum bit function

$s_n = a_n \oplus b_n \oplus c_n$

and the carry-out bit that can be computed from

$c_{n+1} = a_n.b_n + (a_n \oplus b_n). c_n$

Suppose that we want to add two 4-bit words as described by

where $c_4$ is the carry-out bit. Since the n-th sum requires uses the (n-l)-th carry bit, the simplest way to construct a 4-bit parallel adders is using the ripple carry scheme drawn in Figure where the full adder cells are connected to directly provide the carry bit to the next FA unit. The latency associated with obtaining the total sum word $s_3.s_2.s_1.s_0$ and the carry-out bit $c_4$ is due to the fact that all of the carry bits are created in sequence from $c_1 to c_4$ and the observation that the output sum bit $s_n$ is not valid until the carry-in bit $c_n$ from the (n-1) full adder is valid.

The carry look-ahead algorithm provides an alternate approach to constructing parallel adders by calculating the carry bits using separate circuits, and then feeding them to logic gates that produce the sum bits. The basis for the CLA is obtained by studying the conditions that lead to a value of $$c_{n+1} = 1 We see immediately that the OR operation in

$c_{n+1} = a_n.b_n + (a_n \oplus b_n) . c_n$

shows that a carry-out bit with a value of 1 can be “created” in two ways. First,$c_{n+1} = 1$ if the inputs satisfy $a_n.b_n = 1$; this is called a carry generation, since the carry-out is “generated” by the input bits of the word itself. This is illustrated in Figure (a). The second case that causes $c_{n+1} = 1$ is where $(a_n \oplus b_n) = 1$ AND the input carry bit has a value of $c_n = 1$ from the previous (n-l)-st unit; this is called a carry propagation since we can view the input carry $c_n = 1$ as being propagated through the unit to the output as in Figure.

The CLA algorithm is based on these simple observations. To develop the basic equations, we define the generate bit $g_n$ by

$g_n = a_n.b_n$

and the propagate bit $p_n$ as

$p_n = a_n \oplus b_n$

The carry-out bit is then given by

$c_{n+1} = g_n + p_n.c_n $

and the sum is calculated using

$s_n = p_n \oplus c_n$

for each bit in the word.

Using the CLA approach leads to the block diagram for a 4-bit adder that is drawn in Figure. The input words are denoted by $a=(a_3a_2a_1a_0)$ and $b=(b_3b_2b_1b_0)$ and the carry-in bit into the 0-th stage is labelled as $c_{in}$. The first logic network uses $a_3a_2a_1a_0$ and $b_3b_2b_1b_0$ to calculate the generate and propagate bits, $g_3g_2g_1g_0$ and $p_3p_2p_1p_0$ respectively. These are then fed to a logic network that is dedicated to calculating the carry bits $c_4c_3c_2c_1$,where we note that

$c_0 = c_{in}$

defines the carry-in bit. The outputs from this unit are then used to find the result $s_3s_2s_1s_0$. The carry-out bit

$c_4 = c_{out}$

is used to indicate overflow, or as the carry-in bit to the next group of a larger word. The application of MODL circuits to the CLA network can be seen by examining the equations used to compute the carry bits. The carry-out bit $c_1$ for the n = 0 bit position is given by

$c_1 = g_0 + p_0c_0 = g_0 + p_0c_{in} $

and is used as an input by stage 1. Since the carry-out bit $c_2$ from stage 1 is given by

$c_2 = g_1 + p_1c_1$

we may substitute for $c_1$ to arrive at

$c_2 = g_1 + p_1c_1 = g_1 + p_1(g_0 + p_0c_0) = g_1 + p_1g_0 +p_1p_0c_0$

This shows that $c_2$ can be computed solely from the generate and propagation bits. In the same manner,$c_3$ is given by

$c_3 = g_2 + p_2c_2 = g_2 + p_2( g_1 + p_1g_0 +p_1p_0c_0) = g_2 + p_2 g_1 +p_2 p_1g_0 +p_2p_1p_0c_0 $

while

$c_4 = g_3 + p_3c_3 = g_3 + p_3( g_2 + p_2 g_1 +p_2 p_1g_0 +p_2p_1p_0c_0) = g_3 + p_3 g_2 +p_3 p_2 g_1 +p_3 p_2 p_1g_0 +p_3p_2p_1p_0c_0$

gives the carry-out bit $c_{out}$ from the 4-bit unit. These equations show explicitly that each bit can be calculated by ANDing generate and propagate factors together with the nesting required for an MODL circuit.