Binary adders provide the basic connection between Boolean operations and arithmetic. They are commonly used for comparing different technologies or design styles since they are of reasonable importance and complexity.

Figure shows the basic symbol and function table for a full-adder circuit that uses the inputs $a_n$ and $b_n$ and a carry-in bit $c_n$ to produce the sum bit $s_n$ and the carry-out bit $c_{(n+1)}$ The most common SOP expressions obtained directly from the table entries are given by

$s_n = a_n \oplus b_n \oplus c_n$

$c_{n+1} = a_n.b_n + c_n (a_n \oplus b_n)$

as is easily verified by examining the entries that yield a result of 1 for each function. Although it is possible to create the adder circuits from these equations, they are not in AOI form and so do not admit directly to series-parallel logic design. To construct a circuit with this form, we first modify the expressions so that both $s_n$ and $c_{n+1}$ have AOI form, and then use the structured logic design of the previous section.

Let us rewrite the expression for the carry-out bit as

$c_{n+1} = a_n.b_n + c_n (a_n + b_n)$

where we have changed the XOR function to an OR function; this still yields the same result due to the fact that the first term is $a_n.b_n$ The equation for the sum bit can be expanded and rearranged to

$s_n = a_n.b_n.c_n + (a_n + b_n + c_n) . \bar{c_{n+1}} $

so that it uses the carry-out bit as an input. The AOI logic diagrams for both the sum and the carry-out are shown in Figure. Note that the upper (carry-out) and lower (sum) networks are very similar in that they both have OAOI structuring. This allows us to create the series-parallel CMOS circuits shown in Figure for both sections of the full adder; FET placement has been accomplished by using the standard rules. This circuit is straightforward. Note, however, that both gates have somewhat long pFET chains, which may result in a slow response.