Usually a VLSI chip receives one or more primary clock signals from an external clock chip and, in turn, generates necessary derivatives for its internal use. It is often necessary to use two non-overlapping clock signals. The logical product of such two clock signals should be zero at all times. Figure shows a simple circuit that generates CK- 1 and CK-2 from the original clock signal CK. Figure shows a clock decoder circuit that takes in the primary clock signals and generates four phase signals.