The output circuits of VLSI chips are designed to be tristable as shown in Fig. The circuit implementation (b) requires more transistors (12 transistors) than the circuit implementation (c), in which only four transistors are required if polarity is ignored. In terms of silicon area, however, the implementation in (b) may require less than the circuit in (c) since the last-stage transistors have to be sized large to provide sufficient current sinking and sourcing capability and also to reduce delay times.

Unfortunately, such a requirement demands a high rate of change in the current di/dt and can cause significant on-chip noise problems due to the L(di/dt) drop across the bonding wire connecting the output pad to the package.

In high-end microprocessor chips with 32 bits or higher number of data bus lines, the noise problem can be significantly escalated if all output drivers are driven simultaneously. In such cases, it is desirable to stagger the switching times with built-in delays in the clock distribution network, which amounts to reducing the noise at the expense of chip speed.

An interesting circuit technique for reducing di/dt is shown in Fig. This circuit requires an additional strobe signal and hence, complicates the timing design, but reduces the magnitude of di/dt significantly.

The role of two nMOS transistors controlled by the strobe signal (ST) is to precharge the gate potentials of the last-stage driver transistors at an approximate midpoint between the initial and final potentials of the load capacitor. For instance, if r =1 for the pMOS and nMOS driver pair, then when ST is high, the gate voltages can be precharged to VDD/2 before CK goes to high.

Another technique for resolving the output driver problem is to adopt a basic driver circuit that sends out only changes in the data pattern, as shown in Fig. With a delay element, the circuit produces pulses at nodes B and C only when the polarity of the input signal changes. As a result the driver transmits only differential signals rather than full digital waveforms. As shown in Fig.(b), the reference output voltage level is maintained at VDD/2 during the quiescent periods, which are equivalent to tristate periods. The output driver uses a phase splitter to generate differential pairs. The corresponding receiver circuit has to sense, latch, and level-shift the differential data. The circuit shown in Fig. performs these functions.