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Write short note on advantages and disadvantages of PLL

written 5.9 years ago by hetalgosavi • 1.7k

modified 4.6 years ago by prashantsaini • 0

cmos vlsi design

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written 5.7 years ago by hetalgosavi • 1.7k

1. PLLs have disadvantages that make their use in high-speed designs problematic, particularly when both high performance and high reliability are required. The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations in temperature, supply voltage, and manufacturing process affect the stability and operating performance of PLLs.
2. DLLs (Delay Locked Loop), however, are immune to these problems. A DLL in its simplest form inserts a variable delay line between the external clock and the internal clock. The clock tree distributes the clock to all registers and then back to the feedback pin of the DLL.
3. The control circuit of the DLL adjusts the delays so that the rising edges of the feedback clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked, and both the input buffer delay and the clock skew are reduced to zero.
4. Advantages:
5. Precision
6. Stability
7. power management
8. noise sensitivity
9. jitter performance.
10. Its disadvantages are several. First, the DLL circuit operates in an open loop configuration. It has no capability for automatically tracking input frequency or phase changes with variations in temperature, operating voltage, etc.
11. Second, the DLL circuit is single ended rather than differential, so it will be strongly subject to variations in supply voltage.
12. Third, the loop depends for its timing on capacitance and resistance values, which will vary with temperature and operating voltage.

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