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Explain in detail charge pump PLL

written 5.9 years ago by hetalgosavi • 1.7k

modified 4.6 years ago by prashantsaini • 0

cmos vlsi design

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written 5.7 years ago by hetalgosavi • 1.7k

• The charge pump circuit senses the transition at input and output, detects phase or frequency differences, and activates the charge pump accordingly.
• When the input and output frequencies are sufficiently close, the PFD (Phase Frequency Detector) operates as the phase detector, performing phase lock operations.
• The loop locks when the phase difference drops to zero and the charge pump remains relatively idle.
• Ignoring the narrow reset pulse on $Q_A$ and $Q_B$ and assume that Φout - Φin drops to zero, the PFD simply produces $Q_A$ = $Q_B$ = 0
• The charge pump thus remains idle and Cp sustains a constant control voltage.
• The charge pump PLL responds to only excess phase of waveform.

• The phase comparison is performed in every cycle, but the VCO phase and frequency cannot drift substantially.

  

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