Draw and explain charge pump circuit.

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written 5.7 years ago by

hetalgosavi • 1.7k

The phase-locked loop (PLL) is one of the key building blocks in many communication systems; providing a means for maintaining timing integrity and clock synchronization. The PLL can be used in various applications such as timing extraction from data streams, jitter mitigation and frequency synthesis.
The CP-PLL derives its name from the fact that the phase detector (PD) output is a current source as opposed to a voltage source and "pumps" current into and out of the loop-filter.
The charge-pump (Fig. a) consists of a set of current sources with magnitudes of IP1 and IP2 amps respectively. In most cases the current sources are symmetrical thus IP1 = IP2 = IP.
One source is connected to the positive supply rail while the other is connected to the negative supply rail. The sources are separated by two switches S1 and S2.
The output of the phase detector provides the gating signals U (up) and D (down) which turn on S1 and S2 respectively. The phase detector is designed such that switches are never on simultaneously.
When U is high and D is low then S1 is on and S2 is off which causes current to flow out of the pump and into the loop-filter. When U is low and D is high then Q1 is off and Q2 is on which causes current to flow out of loop-filter and into the pump.
A representative CMOS charge-pump circuit is shown in Fig. (b) and is similar to the output stage of the current starved inverter. The VP_BIAS and VN_BIAS voltages set the positive and negative charge-pump currents respectively.

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