written 5.9 years ago by | • modified 5.7 years ago |
Mumbai University > Electronics and Telecommunication > Sem 4 > Microprocessor and peripherals
written 5.9 years ago by | • modified 5.7 years ago |
Mumbai University > Electronics and Telecommunication > Sem 4 > Microprocessor and peripherals
written 5.7 years ago by |
Whenever microprocessor is interrupted the following action takes place.It is known as interrupt sequence.For example: Consider type 35 ISR, The following action takes place,
003FF | CSH |
---|---|
003FE | CSL |
003FD | IPH |
003FC | IPL |
$\bigg\uparrow$ | |
00003 | CSH |
00002 | CSL |
00001 | IPH |
00000 | IPL |
(i) Push contents g flag register, CS And IP into the stack memory pointed by SP.Now SP is decremented by 6.
(ii) Trap flag (TF) is stored temporarily
(iii) TF and IF are cleared i.e TF=0 and IF=0
(iv) Physical address of IVT is calculated an follows
PA= $4*35$ = $(140)_{10}$ = $(8C)_{10}$ = $(0008C)_{10}$
The content of 0008C, 0008D is placed in IP, then contents of 0008E, 0008F is placed in CS. Now, physical address of ISR is calculated by using content of CS and IP.
(v) Microprocessor begins to execute ISR.
(vii) At the end of ISR, The instruction RET is executed. Now , microprocessor comes back to main program by pointing the contents of memory pointed by SP into IP, CS, FR (Flag register), Now , SP is incremented by 6.
(vii) Microprocessor continues to main program.