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Mumbai University > Computer Engineering > Sem 8 > Parallel & Distributed System
written 6.0 years ago by | modified 5.7 years ago by |
Mumbai University > Computer Engineering > Sem 8 > Parallel & Distributed System
written 5.7 years ago by |
Dynamic scheduling is where the hardware rearranges the instruction execution to reduce the stalls.
Dynamic scheduling offers several advantages:
These advantages are gained at a cost of a significant increase in hardware complexity.
A major limitation of the pipelining techniques is that they use in-order instruction issue: if an instruction is stalled in the pipeline, no later instructions can proceed. Thus, if there is a dependency between two closely spaced instructions in the pipeline, it will stall.
For example:
DIVD | F0, F2, F4 |
---|---|
ADDD | F10, F0, F8 |
SUBD | F12, F8, F14 |
SUBD instruction cannot execute because the dependency of ADDD on DIVD causes the pipeline to stall; yet SUBD is not data dependent on anything in the pipeline. This is a performance limitation that can be eliminated by not requiring instructions to execute in order.
Scoreboarding is a technique for allowing instructions to execute out of order when there are sufficient resources and no data dependencies.
The goal of a scoreboard is to maintain an execution rate of one instruction per clock cycle (when there are no structural hazards) by executing an instruction as early as possible. Thus, when the next instruction to execute is stalled, other instructions can be issued and executed if they do not depend on any active or stalled instruction. The scoreboard takes full responsibility for instruction issue and execution, including all hazard detection.
Every instruction goes through the scoreboard, where a record of the data dependencies is constructed; this step corresponds to instruction issue and replaces part of the ID step in the DLX pipeline. The scoreboard then determines when the instruction can read its operands and begin execution.