Subject: Basic VLSI Design

Topic: Semiconductor Memories

Difficulty: Medium

• Consider the first 4-bit X 4bit memory array as shown in Figure below. Here, each column consists of a pseudo nMOS NOR gate driven by some of the row signals, i.e., the word line.

  

• Only one word line is activated at a time by raising its voltage to VDD, while all other rows are held at a low voltage level.

• If an active transistor exists at the cross point of a column and the selected row, the column voltage is pulled down to the logic LOW level by that transistor.
• If no active transistor exists at the cross point, the column voltage is pulled HIGH by the pMOS load device.

• Thus, a logic "1"-bit is stored as the absence of an active transistor, while a logic "0"-bit is stored as the presence of an active transistor at the cross point. The truth table is shown below.

  

• Figure below shows nMOS transistors in a NOR ROM array, forming the intersection of two metal lines and two polysilicon word lines.

• To store a "0"-bit at a particular address location, the drain diffusion of the corresponding transistor must be connected to the metal bit line via a metal-to-diffusion contact. Omission of this contact, on the other hand, results in stored "1"-bit.