Subject: Basic VLSI Design

Topic: Semiconductor Memories

Difficulty: Medium

• A low-power SRAM cell may be designed simply by using cross-coupled CMOS inverters. The possible drawback of using CMOS SRAM cells, on the other hand, is that the cell area tends to be slightly larger in order to accommodate the n-well for the pMOS transistors and the polysilicon contacts.
• The circuit structure of the full CMOS static RAM or 6T RAM cell has pMOS column pull-up transistors on the complementary bit lines.
• The memory cell consists of a simple CMOS latch (two inverters connected back- to-back), and two complementary access transistors (M3 and M4). The cell will preserve one of its two possible stable states, as long as the power supply is available.
• The access transistors are turned on whenever a word line (row) is activated for read or write operation, connecting the cell to the complementary bit-line columns.
• The most important advantage of this circuit topology is that the static power dissipation is very small; essentially, it is limited by the leakage current of the pMOS transistors. A CMOS memory cell thus draws current from the power supply only during a switching transition. The low stand-by power consumption has certainly been a driving force for the increasing prominence of high-density CMOS SRAMs.
• Other advantages of CMOS SRAM cells include high noise immunity due to larger noise margins, and the ability to operate at lower power supply voltages than, for example, the resistive-load SRAM cells.

*Note - in addition explain Read and Write operation of 6T RAM.