Subject: Digital System Design

Topic: Programmable Logic Devices

Difficulty: High

CPLD — a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. Alternative names (that will not be used in this paper) sometimes adopted for this style of chip are Enhanced PLD (EPLD),

Super PAL, Mega PAL, and others.

A CPLD comprises multiple circuit blocks on a single chip, with internal wiring re­ sources to connect the circuit blocks . Each circuit block is similar to a PLA or a PAL; we will refer to the circuit blocks as PAL-like blocks. An example of a CPLD is given in Figure

It includes four PAL-like blocks that are connected to a set of interconnection wires. Each PAL-like block is also connected to a subcircuit labeled //0 block, which is attached to a number of the chip's input and output pins.

Figure shows an example of the wiring structure and the connections to a PAL-like block in a CPLD. The PAL-like block includes 3 macrocells (real CPLDs typically have about 16 macrocells in a PAL-like block), each consisting of a four-input OR gate (real CPLDs usually provide between 5 and 20 inputs to each OR gate). The OR-gate output is connected to another type of logic gate that we have not yet introduced. It is called an Exclusive-OR (XOR) gate. The behavior of an XOR gate is the same as for an OR gate except that if both of the inputs are 1, the XOR gate produces a 0.