Write VHDL code for Fibonacci Series Generator.

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written 6.1 years ago by

vedantchikhale • 860

Diagram:-

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Simulation Output:-

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Code:-

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ENTITY fibonacci IS
GENERIC (N: INTEGER := 16); ------number of bits
PORT (clk, rst : IN BIT;
fibo_series : OUT INTEGER RANGE 0 TO 2**N-1);
END fibonacci;
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ARCHITECTURE fibonacci OF fibonacci IS
SIGNAL a,b,c: INTEGER RANGE 0 TO 2**N-1;
BEGIN
PROCESS (clk,rst)
BEGIN
IF (rst='1') THEN
b <= 1;
c <= 0;
ELSIF (clk'EVENT AND clk-'1') THEN
c <= b;
b <= a;
END IF;
a <= b +c;
END PROCESS;
fibo_series <= c;
END fibonacci;

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