In asynchronous counter, a clock pulse drives FF0. Output of FF0 drives FF1 which then drives the FF2 flip flop. All J and K inputs are connected to Logic 1. Therefore, each flip flop will toggle with negative transition at its clock input.

The 3 bit MOD-8 asynchronous counter consists of 3 JK flipl flops. Overall propagation delay time is the sum of individual delays. Initially all flip flops are reset to produce 0. The output conditions is Q2Q1Q0 = 000.

When the first clock pulse is applied, the FF0 changes state on its negative edge. Therefore, Q2Q1Q0 = 001. On the negative egde of second clock pulse flip flop FF0 toggles. Its output changes from 1 to 0. This being negative change, FF1 changes state. Therefore, Q2Q1Q0 = 010. Similarly, the output of flipflop FF2 changes only when there is negative transition at its input when fourth clock pulse is applied.

The output of the flip flops is a binary number equivalent to the number of clock pulses received. The output conditions are as shown in the truth table.

On the negative edge of eighth pulse, counter is reset.

the counter acts as a frequency divider. FF0 divides clock frequency by 2, FF1 divides clock frequency by 4, FF2 divides clock frequency by 8. If n flip flops are cascaded, we get $2^n$ output conditions.

the largest binary number counted by n cascaded flip flops has a decimal equivalent of $2^n-1$. MOD-8 counter has count of the largest binary number 111 which has decimal equivalent of $2^3-1=7$