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VHDL Code for Full Subtractor
1 Answer
written 6.1 years ago by |
Diagram:-
Truth Table:-
Formulae:-
Difference = A XOR B XOR C
Borrow = A'.B + B.C + A'.C
Code:-
-------- Full Subtractor with STD_LOGIC_VECTOR: --------
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
-------------------------------------------------------
ENTITY Full Subtractor IS
GENERIC (N: INTEGER := 16); --- number of input bits
PORT (a,b,c: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0):
diff, bor: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0));
END Full Subtractor;
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ARCHITECTURE Full Subtractor OF Full Subtractor IS
BEGIN
diff <= a XOR b XOR c;
bor <= ((NOT a AND b) OR (b AND c) OR (NOT a AND c));
END Full Subtractor;