CPLD

The figure shows the block diagram of a complex programmable logic device (CPLD). It consists of a number of PAL-Like Blocks, I/O blocks, and a set of interconnection wires. The PAL-Like Blocks are connected to a set of interconnection wires and each block is also connected to an I/O block to which a number of chip's input and output pins are attached.

A PAL-Like Block usually consists of about 16 macrcells. Each macrocell consists of an AND-OR configuration, an EX-OR gate, a FLIP-FLOP,a multiplexer and a tri-state buffer. Each AND-OR configuration usually consists of 5-20 AND gates and an OR gate with 5-20 inputs. An EX-OR gate is used to obtain the output of OR gate in inverted or non-inverted form depending upon its select input (1 or 0). The tri-state buffer acts as a switch which enables the chip's pin is used as an input pin, an external source can drive a signal on to the pin which can be connected to other macrocells using the interconnection wiring. When used as an input pin, the macrocell becomes redundant and it is wasted.

FPGA

Over the years, programmable arrays have increased in size and complexity, and highly configurable output macrocell have been added to increase their flexibility and expandability. To increase the effective size and to add more functionality in a single programmable device, alternative architectures have been developed which are known as field-programmable gate arrays (FPGA). The logic densities of FPGAs are much higher than those of CPLDs. They range in size from 10,000 to a few hundreds of thousands equivalent gates. From modern standards digital circuits with hundreds of thousands of gates is not too large. FPGA devices support implementation of relatively large logic circuits.

The FPGAs do not contain AND, OR planes, instead they provide logic blocks for implementation of the required digital functions.

An FPGA is composed of a number of relatively independent configurable logic modules, configurable I/O cells, and programmable interconnection paths (known as routing channels). All the resources of the device are uncommitted and that these must be selected, configured and interconnected by a user to form a logic circuit for his application.

FPGA differ primarily in the size and configuration of their logic modules and interconnection requirements. FPGAs with larger logic modules may not be sufficiently utilized, thereby wasting the logic modules for performing simple logic functions. Use of smaller logic modules leads to much larger number of interconnect paths in the device causing significant propagation delay as well as consuming large percentage of the FPGA's area. The optimal logic module size and interconnect requirements are highly dependent on the application that is being implemented in FPGA. For a given FPGA device, there are many possible ways to interconnect the resources required by an application.