SRAM

Memory Read:-

The method for reading the SRAM cell consists of first precharging both Bit Lines to VDD, which are then left floating. Next, WL is asserted, causing one of the BLs to be pulled down. This procedure is illustrated in figure which shows q = '0' and q' = '1' as the current contents of the SRAM cell. The latter causes M1 to be ON and M2 to be OFF, while the former causes M3 to be OFF and M4 to be ON. After bit and bit' have been both precharged to '1' and left floating, the access transistors, M5 and M6, are turned ON by the respective WL. Because M3 is OFF, the BL corresponding to bit' will remain high, while the other will be pulled down (because M1 is ON), hence resulting in bit = '0' and bit' = '1' at the output.

This protection, called read stability, is achieved with M1 stronger (that is, with a larger channel width to- length ratio) than M5. A minimum-size transistor can then be used for M5 (and M6), while a wider channel (typically around twice the width of M5) is employed for M1 (and M3).

Memory Write:-

The memory-write procedure is illustrated in figure(a) and (b). Suppose that the SRAM cell contains q = '0', which we want to overwrite with a '1'. First, bit = '1' and bit' = '0' are applied to the corresponding BLs, then WL is pulsed high. Due to the read stability constraint, M5 might not be able to turn the voltage on node q high enough to reverse the stored bits, so this must be accomplished by M6. This signifies that M6, in spite of M4 being ON, should be able to lower the voltage of q' sufficiently to turn M1 OFF (that is, below M1’s threshold voltage, ~0.5 V), or, at least, well below the transition voltage (VTR) of the M1–M2 inverter. For this to happen, the channel resistance of M6 must be smaller than that of M4 (that is, M6 should be stronger than M4). Because M6 is nMOS and M4 is pMOS (which by itself guarantees a factor of about 2.5 to 3 due to the higher charge mobility of nMOS transistors), same-size transistors suffice to attain the proper protection. In summary, M2, M4, M5, and M6 can all be minimum size transistors, while M1 and M3 must be larger.

DRAM

Memory Read:-

To read data from this memory, fi rst the BL is precharged to VDD/2 then is left floating. Next, the proper WL is asserted, causing the voltage of BL to be raised (if a '1' is stored) or lowered (when the cell contains a '0').

Memory Write:-

To write data into the DRAM cell, the bit values must be applied to the bit lines, then the proper word line is pulsed high, causing the capacitors to be charged (if bit = '1') or discharged (if bit = '0'). Note that, due to the threshold voltage (VT) of the nMOS transistor, Ccell is charged to VDD – VT instead of VDD.