Draw and interface diagram of 8086 and 8087 NDP, also explain various interface signals and co-processor working with host processor.

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written 6.2 years ago by

meghalikalyankar • 2.3k

Interfacing of 8087 and 8086

Co-processor (8087) is connected to 8086, 8086 operates in Maximum Mode. Hence MN/(MX) ̅ is grounded.
8284 provides the common CLK, RESET, READY signals, 8282 are used to latch the address, 8286 are used as data transreceivers, 8288 generates control signals using S2, S1, S0 as input from the currently active processor, 8259 PIC is used to accept the interrupt from 8087 and send it to the µP.
Only 8086 can fetch instructions, but these instructions also enter 8087. 8087 treats 8086 instructions as NOP.
ESC is used as a prefix for 8087 instructions. When an instruction with ESC prefix (5 MSB bits as 11011) is encountered, 8087 is activated. The ESC instruction is decoded by both 8086 and 8087.
If ESC is present 8087 executes the instruction and 8086 discards it. If ESC is not preset then 8086 executes the instruction and 8087 discards it.
During execution, if 8087 needs to read/write more data (operands) from the memory, then it does so by stealing bus cycles from the µP in the following manner: The (RQ) ̅ /(GT) ̅ of 8087 is connected to (RQ) ̅ /(GT) ̅ of the µP.
8087 gives an active low Request pulse. 8086 completes the current bus cycle and gives the grant pulse and enters the Hold state. 8087 uses the shared system bus to perform the data transfer with the memory. 8087 gives the release pulse and returns the system bus back to the µP.
If 8086 requires the result of the 8087 operation, it first executes the WAIT instruction. WAIT makes the µP check the (TEST) ̅ pin. If the (TEST) ̅ pin is high (8087 is BUSY), then the µP enters WAIT state. It comes out of it only when TEST is low (8087 has finished its execution). Thus 8086 get the correct result of an 8087 operation.

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