State purpose of interfacing 8259(PIC) to 8086. Explain interfacing of 8086(minimum mode) and 8259 (single mode).

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meghalikalyankar • 2.3k

PIC 8259 is a Programmable Interrupt Controller that can work with 8085, 8086 etc. It is used to increase the number of interrupts.
A single 8259 provides 8 interrupts while a cascaded configuration of 1 master 8259 and 8 slave 8259s can provide up to 64 interrupts.
8259 can handle edge as well as level triggered interrupts. It has a flexible priority structure. Its interrupts can be masked individually.
The Vector address of the interrupts is programmable. In a cascaded configuration, each 8259 has to be individually initialized, master as well as each slave.

Interfacing of 8259 with 8086

In single mode 8259 can accept 8 interrupts. Whenever a device interrupts 8259, 8259 will interrupt the µP on INTR pin. Hence, first the INTR signal of the µP should be enabled using the STI instruction. 8259 is initialized by giving ICW1 and ICW2 (compulsory) and ICW4 (optional). Note that ICW3 is not given as Single 8259 is used. OCWs are given if required.
Once 8259 is initialized, the following sequence of events takes place when one or more interrupts occur on the IR lines of the 8259.

1) The corresponding bit for an interrupt is set in IRR.

2) The Priority Resolver checks the 3 registers: IRR (for highest interrupt request) IMR (for the masking Status) InSR (for the current level serviced) and determines the highest priority interrupt. It sends the INT signal to the µP.

3) The µP finishes the current instruction and acknowledges the interrupt by sending the first INTA pulse. On receiving the first INTA signal, the corresponding bit in the InSR is set (indicating that now this interrupt is in service) and the bit in the IRR is reset (to indicate that the request is accepted).

4) The µP sends the second INTA pulse to 8259. In response to the 2nd INTA pulse, 8259 sends the one byte Vector Number N to µP. Now the µP multiplies N x 4, to get the values of CS and IP from the IVT.

5) In the AEOI Mode the InSR bit is reset at this point, otherwise it remains set until an appropriate EOI command is given at the End of the ISR.

6) The µP pushes the contents of Flag Register, CS, IP, into the Stack, Clears IF and TF and transfers program to the address of the ISR, then ISR starts executing.

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