DMA controller has four modes for data transfer:

1. Single Byte Transfer Mode/ Cycle Stealing

• Once the DMAC becomes the bus master, it will transfer only ONE BYTE and return the bus back to the microprocessor. As soon as the microprocessor performs one bus cycle, DMAC will once again take the bus back from the microprocessor.
• Both DMAC and microprocessor are constantly stealing bus cycles from each other. It is the most popular method of DMA, because it keeps the microprocessor active in the background.
• After a byte is transferred, the CAR and CWCR are adjusted accordingly. The system bus is returned to the µP. For further bytes to be transferred, the DREQ line must go active again, and then the entire operation is repeated.

2. Block Transfer Mode.

• In this mode, the DMAC is programmed to transfer all the bytes in one complete DMA operation. After a byte is transferred, the CAR and CWCR are adjusted accordingly.

• The system bus is returned to the µP, only after all the bytes are transferred. i.e. TC is reached or EOP signal is issued. It is the fastest form of DMA but keeps the microprocessor inactive for a long time.

• The DREQ signal needs to be active only in the beginning for requesting the DMA service initially. Thereafter DREQ can become low during the transfer.

3. Demand Transfer Mode

• It is very similar to Block Transfer, except that the DREQ must active throughout the DMA operation.

• If during the operation DREQ goes low, the DMA operation is stopped and the busses are returned to the µP.

• In the meantime, the µP can continue with its own operations. Once DREQ goes high again, the DMA operation continues from where it had stopped.

4. Cascade Transfer Mode

• In this mode, more than one DMACs are cascaded together. It is used to increase the number of devices interfaced to the µP. Here we have one Master DMAC, to which one or more Slave DMACs are connected.

• The Slave gives HRQ to the Master on the DREQ of the Master, and the Master gives HRQ to the µP on the HOLD of the µP.