• An interrupt is a special condition that arises during the working of a µP. The µP services it by executing a subroutine called Interrupt Service Routine (ISR). There are two types of interrupts for 8086:

Hardware Interrupts: These interrupts occur as signals on the external pins of the µP. 8086 has two pins to accept hardware interrupts, NMI and INTR.

Software Interrupts: These interrupts are caused by writing the software interrupt instruction INTn where “n” can be any value from 0 to 255 (00H to FFH). Hence all 256 interrupts can be invoked by software.

• The addresses of all ISR are stored in Interrupt Vector Table (IVT). It contains ISR address for the 256 interrupts. Each ISR address is stored as CS and IP.

• Each ISR address is of 4 bytes (2–CS and 2-IP), each ISR address requires 4 locations to be stored. There are 256 interrupts: INT 0 … INT 255. Therefore, the total size of the IVT is 256 x 4 = 1KB.

• The first 1KB of memory, address 00000 H to 003FF H, are reserved for the IVT. Whenever an interrupt INT N occurs, µP does N x 4 to get values of IP and CS from the IVT and hence perform the ISR.

Interrupts are classified into three groups:

1. Dedicated Interrupts (INT 0 … INT 4)

   i). INT 0 (Divide Error): This interrupt occurs whenever there is division error i.e. when the result of a division is too large to be stored. This condition normally occurs when the divisor is very small as compared to the dividend or the divisor is zero. Its ISR address is stored at location 0 x 4 = 00000H in the IVT.

ii). INT 1 (Single Step): The µP executes this interrupt after every instruction if the TF is set. It puts µP in Single Stepping Mode i.e. the µP pauses after executing every instruction. This is very useful during debugging. Its ISR address is stored at location 1 x 4 = 00004H in the IVT.

iii) INT 2 (Non Maskable Interrupt): The µP executes this ISR in response to an interrupt on the NMI line. Its ISR address is stored at location 2 x 4 = 00008H in the IVT.

iv). INT 3 (Breakpoint Interrupt): This interrupt is used to cause Breakpoints in the program. It is caused by writing the instruction INT 03H or simply INT. It is useful in debugging large programs where Single Stepping is inefficient. Its ISR address is stored at location 3 x 4 = 0000CH in the IVT.

v) INT 4 (Overflow Interrupt): This interrupt occurs if the Overflow Flag is set AND the µP executes the INTO instruction (Interrupt on overflow). It is used to detect overflow error in signed arithmetic operations. Its ISR address is stored at location 4 x 4 = 00010H in the IVT.

2. Reserved Interrupts
INT 5 to INT 31, these levels are reserved by INTEL to be used in higher processors like 80386, Pentium etc. They are not available to the user.

3. User defined Interrupts
INT 32 to INT 255, these are user defined, software interrupts. ISRs for these interrupts are written by the users to service various user defined conditions. These interrupts are invoked by writing the instruction INT n. Its ISR address is obtained by the µP from location n x 4 in the IVT.