a): ¯TEST:

• It is an active low input line dedicated for 8087 Co-processor. It is used in Maximum Mode whenever the Co-Processor is busy it makes this pin HIGH. µP samples the ¯TEST input only when it encounters the WAIT instruction.
• If the ¯TEST pin is high, the µP enters wait state, till ¯TEST pin becomes low i.e. 8087 is free.

b) ¯RQ0/¯GT0 :

• In Maximum Mode it carries the bi-directional ¯RQ0/¯GT0 signal (Request/Grant).The external bus master ( 8087) sends an active low pulse to request for the system bus.

• In response the 8086 completes the current bus cycle, releases the system bus and sends an active low Grant pulse on the same line to the external bus controller. 8086 gets back the system bus only after external bus master sends an active low release pulse on the same line.

c) ¯LOCK :

• It functions as the ¯LOCK output line. When this signal is active (i.e. low) the external bus master cannot take control of the system bus. It is activated when 8086 executes an instruction with the ¯LOCK prefix, and remains active till next instruction.

• LOCK Prefix: Normally a bus request is serviced after the current machine cycle and an interrupt request is serviced after the current instruction cycle. But if we write LOCK prefix before any instruction, then even if there is a bus request, the bus will be released only after the current instruction. Hence the bus is said to be locked during the instruction.

d) QS0 and QS1:

• These two are output pins are used to indicate the instruction queue status.

e) ¯S0, ¯S1, ¯S2:

It is used to indicate the status of machine cycle