The implementation of FinFET structure in bulk silicon wafers is very attractive due to low cost technology and compatibility with standard bulk CMOS in comparison with SOI FinFET.

If SOI and bulk FinFETs are analyzed by a 3D numerical device simulator, it is observed that bulk FinFET with source/ drain to body junctions shallower than gate – bottom has equal or better subthreshold performance than SOI FinFET.

By keeping the body doping low and junctions shallower than gate – bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.