1) Buffered FET logic (BFL):

• Fastest but highest power approach.

• Two diodes near the output terminal are required to shift the output voltage back to the input level.

• Large power dissipation (typically % mV per gate).

• Large area is required for layout.

• Restricted for small and medium level integration.

2) Schottky diode FET logic (SDFL):

• The level shifting necessitated by the use of d mode FETs is done by using diodes at input stage to provide the logical OR function.

• Power dissipation is about 1 mW per gate.

• The gate delay is twice as large as BFL.

• ICs with as many as 10000 gates can be built in SDFL.

3) Directed coupled FET logic (DCFL):

• Least power consumption in all approaches, less than 0.5 mW per gate.

• Output of basic inverter structure does not involve any diode drops. Because of this no level shifting is required.

• Noise margin is small but gate delay is large than SDFL.

• Due to compact layout and less power dissipation, it allows over 65000 transistors n single chip.