Yield:

Process yield is defined as fraction of acceptable parts among all parts fabricated. Wafer yield is the average number of good chips/wafer.

Wafer yield can be used as process yield. Many factors affect yield including die area, process maturity and number of process steps.

Some defects can be observed by using electronic microscopes but some are detectable only by testing. To estimate VLSI yield, defects are modeled as random phenomenon.

It is difficult to obtain an exact value of yield since the tests are based on fault models that do not detect all defects.

Testing cannot improve process yield. It is only a screening process for bad chips.

Process yield can be improved by:

a) Diagnosis and Repair: Parts that fail can be diagnosed and repaired in some situations. This strategy improves yield but also increases production cost.

b) Process Diagnosis and Correction: Failure analysis determines the root cause and the process are corrected. Therefore this strategy is more cost effective.

Defect Level (DL):

It is defined as the fraction of bad chips that pass final package tests. DL is usually expressed in Defect-Per-Million or DPM. Defect level is used as a quality measure.

Random defects are characterized by two parameters. First is defect density (d) which is the average number of defects per unit area and second is clustering parameter (α)

DL (or reject ratio) is a measure of the effectiveness of the tests. Its objective is to develop a test that reduces the number of outgoing faulty parts.

The DL can be determined from the field return data. Chips are returned if they fail acceptance test, fail system test or fail in the field during a maintenance test.

For commercial VLSI chips, a DL > 500ppm is considered unacceptable.