The VLSI testing process is as follows:

Verification testing, characterization testing and design debug:

a. Verifies correctness of design and test procedure.

b. More common to correct design than test procedure.

Manufacturing testing:

a. Factory testing of all manufactured chips for parametric faults and for random defects.

Acceptance testing (incoming inspection):

a. Customer performs tests on purchased parts to ensure quality

The testing principle is given by –

When the chip is digital, the stimuli are called test patterns or test vectors.

Automatic test equipment (ATE) carries out this process-

b. A powerful computer operating under the control of a test program, a program written in a high level language.

c. Digital signal processor (DSP) used for analog testing.

Chips are automatically fed to the tester through the wafer handler system. A probe card or membrane probe contacts pads of bare or packaged chip.

Types of testing:

i) Verification testing

a. It is performed on new designs and determines if design is correct and meets specifications and is very expensive.

b. AC, DC and functional tests are performed.

c. Probing of internal chip nodes may also be performed.

d. The functional tests may be repeated multiple times.

e. Specialized tools are used, such as scanning electron microscopes (SEM) and electron.

ii) Manufacturing testing

a. This type of testing is referred as go/no-go testing.

b. It determines if all the chips manufactured meet the specifications.

c. Test should cover high percentage of modeled faults.

d. No fault diagnosis, only an outgoing inspection test.

e. Test at speed of application or speed guaranteed by the supplier.

f. The main concern is cost as the tests need to be performed on each chip.

g. Tests need to be less extensive but optimized to give expected quality.

iii) Burn-in testing

a. The chips are subjected to high temperature and elevated voltages, while running entire or subsets of production tests.

b. Some chips that pass production test will fail very quickly thereafter.

c. Burn-in ensures reliability by forcing failure in these "weak" chips.

iv) Incoming inspection

a. They can be similar to production testing. However, they are more comprehensive than production testing.

b. They are tuned to specific systems application.

c. They are often done for a random sample of devices.

d. Sample size depends on device quality and system reliability requirements.

e. Avoids putting defective devices in a system where cost of diagnosis exceeds incoming inspection cost.

v) Wafer sort or probe test

a. This test is performed before wafer is scribed (cut into chips).

b. Test site characterization is also performed during wafer sort.

c. Test structures are tested to characterize the technology including gate threshold, poly sheet resistance, etc.

vi) Packaged device tests

a. Sub-types of tests include:

a) Parametric tests: DC parametric tests include shorts test, opens test, leakage test, etc. AC parametric tests include delay test, setup and hold test, etc.

b) Functional Tests: Test every transistor and wire. They are designed to cover a high percentage of modeled faults. They are long and expensive.

Test specifications and test plan:

The chip specification document initiates test development.

It contains:

Functional characteristics, e.g. algorithm to be implemented, I/O signal characteristics (timing and signal levels), clock rate.

Type of chip, e.g., microprocessor, memory, mixed-signal, etc.

Physical characteristics, e.g., pin assignments, etc.

Technology, e.g., gate array, custom, std cell, etc.

Environmental characteristics, e.g., operating temperature, supply voltage, etc.

Reliability, e.g., acceptance quality level (defects per million, dpm), failure rate per 1,000 hours, noise characteristics.

These are used to derive a test plan, which includes

• Type of test equipment to use, i.e., required clock rate, timing accuracy, etc.

• Types of tests.

• Fault coverage requirements.

Test programming

• The test program, the digital test vectors and the analog test waveforms are needed once the chip is mounted in the tester.

• CAD tools to automate the generation of the test programs.