1. Rising chip clock rates:

The exponentially rising clock rates in last few years indicate several changes in testing over the next 10 years.

• At speed testing –

Stack fault tests covers all or most circuit signals assuming that a faulty signal may be permanently stuck at logic 0 or logic 1. It has been established that this test is more effective when applied at circuits rated clock speed than at a lower speed. For this ATE must operate as fast as or faster than circuit under test (CUT).

• ATE cost –

Semiconductor industry is facing two problems. First, installed test capabilities of many factories around world allows clock rate which are less than the requirement. By the time these systems are replaced with new equipment, clock rates are likely to be even more. Second, the microprocessor clock rate in year 2000 has already approached 1 GHz, exceeding state of art of ATE.

• EMI –

A chip operating in GHz frequency range must be tested for electromagnetic interference.

2. Increasing transistor density:

The doubling of transistors on an integrated circuit every 18 to 24 months has been known as Moore’s law. Such a high number of transistors are leading to several results.

• Test complexity –

As the transistor density increases, test difficulty increases. Test pattern generation computation time, in worst case, rises exponentially with the number of chip primary inputs and with number of on chip flip flops.

• Power dissipation –

Testing must check for power grid IR drop and application of the tests must consider power dissipation.

3. Integration of analog and digital devices onto one chip:

Integration on to one chip eliminates a significant delay but brings new issues of testing mixed signal circuits on one chip.