IC packaging can be divided into following:

Surface-mount packages (plastic or ceramics), Chip scale packaging, Bare die, Through-Hole packages

1. Surface mount packages:

   Surface-mount technology (SMT) is a method for producing electronic circuits in which the components are mounted or placed directly onto the surface of printed circuit boards (PCBs). An electronic device so made is called a surface-mount device (SMD). An SMT component is usually smaller than its through-hole counterpart because it has either smaller leads or no leads at all. It may have short pins or leads of various styles, flat contacts and a matrix of solder balls (BGAs), or terminations on the body of the component.

   i. Chip Carrier Packages (CCP):

   This SMT package type is available in two variations, the leadless chip carrier and the leaded chip carrier. The leadless chip carrier is designed to be mounted directly on the PCB, and it can support a high pin count. The main drawback is the inherent difference in thermal coefficients between the chip carrier and the PCB, which can eventually cause mechanical stresses to occur on the surface of the PCB. The leaded chip carrier package solves this problem since the added leads can accommodate small dimension variations caused by the differences in thermal coefficients

   ii. Quad Flat Packs (QFP):

   This SMT package type is similar to leaded chip carrier packages, except that the leads extend outward rather than being bent under the package body. Ceramic and plastic QFPs with very high pin counts (up to 500) are becoming popular package types in recent years.

   iii. Ball Grid Array:

   The BGA is a package with one face covered (or partly covered) with pins a grid pattern which, in operation, conduct electrical signals between the integrated circuit and the printed circuit board (PCB) on which it is placed. In a BGA the pins are replaced by pads on the bottom of the package, each initially with a tiny ball of solder stuck to it. These solder spheres can be placed manually or by automated equipment, and are held in place with a tacky flux. The device is placed on a PCB with copper pads in a pattern that matches the solder balls. Ball Grid Array uses the underside of the package to place pads with balls of solder in grid pattern as connections to PCB.

2. Chip scale packaging:

   This form of packaging technique is designed to have the size and performance of bare die parts but the handling and testability of packaged device. Flip chips packages include the controlled collapse chip connection (C4), developed by IBM and the direct chip attachment (DCA) developed by Motorola.

3. Bare die:

   Bare or unpacked parts offer smallest size, with no signal delay, associated with the device package. The most common bare die and tape packages include the following

   i. C4PGBA that attaches the IC die to plastic substrate by C$ process.

   ii. Chip on scale package (CSP), a Mitsubishi package where an IC is surrounded by protective covering through which the external electrode bumps on the bottom provide electrical contacts

   iii. Chip on board (COB) where the die is mounted directly on the printed circuit substrate.

   iv. Chip on flex

   v. Demountable tape automated bonding (DTAB)

4. Through-hole packages:

Through hole technology uses holes drilled through the PCB for mounting the components. The component has leads that are soldered to pads on the PCB to electrically and mechanically connect them to the PCB. It can be classified as single inline packages and dual in line packages.

i. A single in-line (pin) package: (SIP or SIPP) has one row of connecting pins. It is not as popular as the DIP, but has been used for packaging RAM chips and multiple resistors a common pin.

ii. Dual In-line Packages (DIP): This PTH package has been the most dominant IC package type for more than 20 years. In microelectronics, a dual in-line package (DIP or DIL), or dual in-line pin package (DIPP) is an electronic component package with a rectangular housing and two parallel rows of electrical connecting pins. The package may be through hole mounted to a printed circuit board or inserted in a socket. DIP has the advantage of low cost but their dimensions can be prohibitive, especially for small, portable products. The maximum pin count of DIP is typically limited to 64.

iii. Pin Grid Array (PGA) Packages: This PTH package type offers a higher pin count (typically 100 to more than 400 pins) and higher thermal conductivity (hence, better power dissipation characteristics) compared to DIPs, especially when a passive or active heat sink is attached on the package. The PGA packages require a large PCB area, and the package cost is higher than DIP, especially for ceramic PGAs.