Once all components are fabricated on a single crystal wafer, they must be electrically isolated from each other. The problem is not encountered indiscrete circuits, because physically all components are isolated. Device isolation is the ability of technology to allow each device to operate independently, of the state of other device.

1) Junction Isolation

The method of isolation is most compatible with the IC processing.

Basically the method involves producing regions of n- type material surrounded by p-type material. Components are then fabricated in different n-type wells.

The p-type material surrounding the wells is given the most negative p potential with respect to all parts of the wafer, thus each well and hence component is electrically isolated from the others by back-to-back diodes.

Isolation between two adjacent transistors in CMOS circuits is necessary to isolate n channel and p channel transistors in order to avoid the undesirable parasitic currents between the transistors.

However, the time required for such isolation technique is considerably longer due to diffusion time taken, which is longer than any of other diffusions.

Isolation diffusion takes an area of the wafer surface which is significant portion of the chip area. From component density consideration, this area is wasted.

Junction isolation method introduces significant parasitic capacitance which degrades circuit performance.

2) Oxide Isolation

Isolation can also be obtained by the formation of individual tubs of active material, which are lined with an oxide layer.

The process is as follows:

1. An n-type silicon slice is masked with SiO2.
2. Anisotropic etching is done to get V-shaped grooves.
3. Highly doped n layer is diffused across entire slice to provide low resistance ohmic contact.
4. Thermal oxide is grown over wafer which act as isolation between single crystal and subsequent polycrystalline silicon which is next deposited to thickness of 250-500 μm.
5. Single crystal side of slice is thinned resulting in a structure shown in figure. Mechanical polishing followed by chemical etching of etch stop layer is commonly used.
6. Resulting slice consist of a series of tubs of single crystal silicon, isolated from each other by $SiO_2$ . Various active components may be fabricated within these tubs as desired.
7. Each tub is lines with $n^+$ layer which provides collector connection with a low paretic resistance.

3) LOCOS

Local Oxidation of Silicon (LOCOS) is the traditional isolation technique.

At first a very thin silicon oxide layer is grown on the wafer, the so-called pad oxide.

Then a layer of silicon nitride is deposited which is used as an oxide barrier.

The pattern transfer is performed by photolithography.

After lithography the pattern is etched into the nitride. The result is the nitride mask as shown in Figure, which defines the active areas for the oxidation process.

The next step is the main part of the LOCOS process, the growth of the thermal oxide. After the oxidation process is finished, the last step is the removal of the nitride layer.

The main drawback of this technique is the so-called bird's beak effect and the surface area which is lost to this encroachment.

The advantages of LOCOS fabrication are the simple process flow and the high oxide quality, because the whole LOCOS structure is thermally grown.

4) Trench Isolation

1. Shallow trench isolation –

Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage between adjacent semiconductor device components.

STI is generally used on CMOS process technology nodes of 250 nanometers and smaller. Older

CMOS technologies and non-MOS technologies commonly use isolation based on LOCOS.

The Shallow Trench Isolation (STI) is the preferred isolation technique for the sub-0.5 μm technology, because it completely avoids the bird's beak shape characteristic.

With its zero oxide field encroachment STI is more suitable for the increased density requirements, because it allows forming of smaller isolation regions.

The STI process starts in the same way as the LOCOS process. The first difference compared to

LOCOS is that a shallow trench is etched into the silicon substrate, as shown in Figure.(a)

After underetching of the oxide pad, also a thermal oxide in the trench is grown, the so-called liner oxide (Figure c).

But unlike with LOCOS, the thermal oxidation process is stopped after the formation of a thin oxide layer, and the rest of the trench is filled with a deposited oxide (Figure d).

Next, the excessive (deposited) oxide is removed with chemical mechanical planarization. At last the nitride mask is also removed. The price for saving space with STI is the larger number of different process steps.

2. Deep trench isolation –

It uses the trenches of fixed width, typically 0.18 to 1 μm in width and 2 to 5 m in width and 2 to 5 μm in depth. Smaller trench widths are particularly attractive for memory application.

It finds application in CMOS image sensors (used in camera).

The process is fabricated by starting from a standard LOCOS structure.

After nitride patterning, the trenches are etched. Trench is typically done by simultaneously depositing $SiO_2$ while etching silicon anisotropically.

This creates small cusp of $SiO_2$ at the top of the trench. The thickness of this cusp increases with time and create desired taper.

The walls cannot undercut the mask and must result in rounded bottom.

Then a field implant is done. The implant is followed by a thin local oxidation.

Finally a layer of polysilicon is deposited and etched back. If polysilicon is thick enough it will fill the groove. Second thermal oxidation can be used to complete the process by oxidizing the upper part of polysilicon in groove.