Subject: Microcontroller and Applications

Topic: ARM Cortex-M3 Architecture

Difficulty: Medium

The Cortex-M3 processor has a fixed memory map as shown in the figure below. This makes it easier to port software from one Cortex-M3 product to another. The memory map definition allows great flexibility so that manufacturers can differentiate their Cortex-M3-based product from others. Some of the memory locations are allocated for private peripherals such as debugging components. They are located in the private peripheral memory region. These debugging components include the following:

Fetch Patch and Breakpoint Unit (FPB)

Data Watchpoint and Trace Unit (DWT)

Instrumentation Trace Macrocell (ITM)

Embedded Trace Macrocell (ETM)

Trace Port Interface Unit (TPIU)

ROM table.

The Cortex-M3 processor has a total of 4 GB of address space. Program code can be located in the code region, the Static Random Access Memory (SRAM) region, or the external RAM region. It is best to put the program code in the code region because with this arrangement, the instruction fetches and data accesses are carried out simultaneously on two separate bus interfaces.

The SRAM memory range is for connecting internal SRAM. Access to this region is carried out via the system interface bus. In this region, a 32-MB range is defined as a bit-band alias. Within the 32-bit-band alias memory range, each word address represents a single bit in the 1-MB bit-band region. A data write access to this bit-band alias memory range will be converted to an atomic READ-MODIFY-WRITE operation to the bit-band region so as to allowa a program to set or clear individual data bits in the memory. The bit-band operation applies only to data accesses not instruction fetches. By putting Boolean information (single bits) in the bit-band region, we can pack multiple Boolean data in a single word while still allowing them to be accessible individually via bit-band alias, thus saving memory space without the need for handling READ-MODIFY-WRITE in software.

Another 0.5-GB block of address range is allocated to on-chip peripherals. Similar to the SRAM region, this region supports bit-band alias and is accessed via the system bus interface. However, instruction execution in this region is not allowed. The bit-band support in the peripheral region makes it easy to access or change control and status bits of peripherals, making it easier to program peripheral control.

Two slots of 1-GB memory space are allocated for external RAM and external devices. The difference between the two is that program execution in the external device region is not allowed, and there are some differences with the caching behaviors.The last 0.5-GB memory is for the system-level components, internal peripheral buses, external peripheralbus, and vendor-specific system peripherals. There are two segments of the private peripheral bus (PPB):

Advanced High-Performance Bus (AHB) PPB, for Cortex-M3 internal AHB peripherals only; this includes NVIC, FPB, DWT, and ITM.

Advance Peripheral Bus (APB) PPB, for Cortex-M3 internal APB devices as well as external peripherals (external to the Cortex-M3 processor); the Cortex-M3 allows chip vendors to add additional on-chip APB peripherals on this private peripheral bus via an APB interface. The NVIC is located in a memory region called the system control space (SCS) Besides providing interrupt control features, this region also provides the control registers for SYSTICK, MPU, and code debugging controlThe remaining unused vendor-specific memory range can be accessed via the system bus interface. Therefore, instruction execution in this region is not allowed.The Cortex-M3 processor also comes with an optionalMPU. Chip manufacturers can decide whether to include the MPU into their products or not.