The programmer’s model:

The processor implements the ARM v7-M architecture. This includes the entire 16-bit Thumb instruction set and the base Thumb-2 32-bit instruction set architecture. The processor cannot execute ARM instructions. The Thumb instruction set is a subset of the ARM instruction set, re-encoded to 16 bits. It supports higher code density and systems with memory data buses that are 16 bits wide or narrower. Thumb-2 is a major enhancement to the Thumb Instruction Set Architecture (ISA). Thumb-2 enables higher code density than Thumb and offers higher performance with 16/32-bit instructions.

Operating modes:

The processor supports two modes of operation, Thread mode and Handler mode:

Thread mode is entered on Reset, and canbe entered as a result of an exception return. Privileged and User (Unprivileged) code can run in Thread mode.

Handler mode is entered as a result of an exception. All code is privileged in Handler mode.

Operating states:

The processor can operate in one of two operating states:

Thumb state is normal execution running 16-bit and 32-bit halfword aligned Thumb and Thumb-2 instructions.

Debug State is the state when in halting debug.

Privileged access and user access:

Code can execute as privileged or unprivileged. Unprivileged execution limits or excludes access to some resources. Privileged execution has access to all resources. Handler mode is always privileged. Thread mode can be privileged or unprivileged.Thread mode is privileged out of reset, but one can change it to user or unprivileged by clearing the CONTROL[0] bit using the MSR instruction. User access prevents:

use of some instructions such as CPS to set FAULTMASK and PRIMASKaccess to most registers in System Control Space (SCS). When Thread mode has been changed from privileged to user, it cannot change itself back to privileged. Only a Handler can change the privilege of Thread mode. Handler mode is always privileged.