Pipelining in DSP Processor

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written 6.1 years ago by

teamques10 ★ 68k

• modified 5.4 years ago

Architectural feature in which an instruction is broken into a number of steps, a separate unit performs each step at the same time usually working on different stage of data. This can be done by processing number of instructions simultaneously.

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Generally one complete instruction start from fetching an instruction and ends with execution of instruction. The total required time period is allocated for different purposes throughout the instructions.
An entire instruction can be divided into number of steps:

1) Fetching instruction from program memory.

2) Decoding of instruction.

3) Operand fetching, which is necessary for execution of instruction.

4) Execution of instruction

5) Save the result.
Now each of the above steps (micro-instruction) can be carried out separately by 5 functional units in CPU. Suppose each micro instruction requires same amount of execution time.
In a conventional processor, CPU processes only one instruction at a time, so each functional unit is busy only for one-fifth time period. But in case of processes which use pipelining all these 5 micro-instructions can be carried out simultaneously in the CPU

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