NAND gate is combination of AND and NOT gate.So the output of and gate gets inverted by the not gate to give the output of NAND gate. The output is high when one of the input is low and is low when all the inputs are high. NAND gate function is also available in the library of IEEE so it can be directly used in the program where there is a need of NAND gate. Program for performing NAND logic between two inputs a and b to give the output y is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nand1 is
Port ( a : in std_logic;
       b : in std_logic;
       y : out std_logic);
end nand1;

architecture nand11 of nand1 is

begin
y<=a nand b;

end nand11;