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Explain Entity in VHLD and write VHDL program for half subtractor cricuit

written 6.3 years ago by teamques10 ★ 69k

modified 4.1 years ago by ninadsail • 10

digital logic design

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written 6.3 years ago by teamques10 ★ 69k

VHDL Code for a Half-Subtractor

Library ieee;
use ieee.std_logic_1164.all;

entity half_sub is
port(a,c:in bit; d,b:out bit);
end half_sub;  

architecture data of half_sub is
begin

d<= a xor c;

b<= (a and (not c));
end data;

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