The maximum mode operation of 8086 up is suitable for designing and multiprocessor systems like.

a] closely coupled system.

b] Loosely coupled system.

c] Tightly coupled system.

The maximum mode pin diagram of 8086.

• In above pin diagram it can be observed that only pin 24.31 will be differing in min.mode and max,mode of 8086 microprocessor.

• These max.mode pins can be described as follows:

1. $\overline{QS_0} \quad \overline{Qs_1}$ : These are Q status pin, which are monitored by 8087 NDP to synchronize with 8086 microprocessor.

2. $\overline{S0}, \quad \overline{S_1}, \quad \overline{S_2}$ : These are status pins initiated with binary coded information about type of access, the up will be performing with memory or IO devices.

3. $\overline {TEST} \ pin$ : It is used in conjunction with WAIT instruction in multiprocessor environment.

4.$ \overline {LOCK} \ pin$ : This output pin of up activated while up is executing an instruction with $ \overline {LOCK}$ prefix.

5. $\overline{RQ} / \overline{GT}$ : There are request/grant pins used by 8087 NDP or 8089 IOP to request for system bus control in multiprocessor environment.

A typical 8086 maximum mode s/m diagram will be as follow:

• In this mode latches are used to demultiplex ADo-A19/S6 of up to obtain address lines A0-A19.

• Transceivers are used to provides two sets of data buses D0 - D7 and D8 - D15.

• The 8284 clock generator is used to provide CLK, RESET AND READY signal for the up as well as for 8087 NDP.

• The 8288 bus controller is responsible for status decoding (on S0 S1 S2) to generate.

a] control signals & (b) command signals.

a] Control signals Like ALE, DEN & DT/$\overline R$ to control the operation of latches & trans receiver.

b] Command signals Like $\overline{MRDC}$,$\overline{MWTC}$ $\overline{DORC}$ and $\overline{IOWC}$ to control read or write access with memory & IO devices in 8086 based system.