ln all of the current mirror circuits considered, the reference current is a function of the applied supply voltages. This implies that the load current is also a function of the supply voltages. In most cases, supply voltage dependence is undesirable. Circuit designs exist in which the load currents are essentially independent of the bias.

Since the PMOS devices are matched, the currents Id1 and Id2 must be equal. Equating the currents in M1 and M2, we find

$I_{D1}=\frac{k'_n}{2}\left(\frac{W}{L}\right)_1(V_{GS1}-V_{TN})^2=I_{D2}=\frac{k'_n}{2}\left(\frac{W}{L}\right)_2(V_{GS2}-V_{TN})^2$ - (1)

Also, Vgs2 = Vgs1 - Id2.R - (2)

Substituting equation (2) in (1) and solving for R, we get

$R=\frac{1}{\sqrt{K_{n1}I_{D1}}}\left(1-\sqrt{\frac{(W/L)_1)}{(W/L)_2}}\right)$

This value of resistance R will establish the drain currents Id1 = Id2. These currents establish the gate-to·source voltage across M1 and the source-to-gate voltage across M3. These voltages, in turn, can be applied to M5 and M6 to establish load currents Io1 and Io2.

The currents Id1 and Id2 are independent of the supply voltages $V^+$ and $V^-$ as long as M2 and M3 are biased in the saturation region. As the difference $(V^+ - V^-)$ increases, the values of Vds2 and Vsd3 increase but the currents remain essentially constant.