Short channel effects are usually seen for devices with channel lengths up to 3 micro meters.

Short channel effects occur due to :-

1) the electric fields tend to increase because the supply voltage has not scaled proportionally.

2) the built-in potential is neither scalable nor negligible.

3) the depth of S/D junctions cannot be reduced easily.

4) the mobility decreases as the substrate doping increases.

5) the subthreshold curve is not scalable.

The various short channel effects are:-

1. Negative Bias Temperature Instability (NBTI) :- In a modern PMOS device when the gate voltage is driven below its source voltage (VSG >0) crucial device parameters, such as the threshold voltage, are observed to shift over time. Historically, both the trapping of holes in oxide defects and the creation of interface states have been suspected to be the cause of the shift. NBTI can be a significant reliability concern in Si02 gate dielectrics due to time and temperature-dependent fluctuations in device parameters during both on and off states of operation. NBTI is also present in NMOS devices but it is considerably more pronounced in the PMOS transistor.

2. Oxide Breakdown :- For reliable device operation, the maximum electric field across a device gate oxide should be limited to 10 MV/cm. This translates into 1 V / 10 Ä of gate oxide. A device with tox of 20 A should limit the applied gate voltages to 2 V for reliable long-term operation.

3. Drain-Induced Barrier Lowering :- Drain-induced barrier lowering (DIBL, pronounced "dibble") causes a threshold voltage reduction with the application of a drain-source voltage. The positive potential at the drain terminal helps to attract electrons under the gate oxide and thus increase the surface potential Vs. In other words VDS helps to invert the channel on the drain side of the device, causing a reduction in the threshold voltage. Since VTHN decreases with increasing VDS, the result is an increase in drain current and thus a decrease in the MOSFET's output resistance.

4. Gate-Induced Drain Leakage :- Gate-Induced Drain Leakage (GIDL, pronounced "giddle") is a term used to describe a component of the drain to substrate leakage current. When the device is in accumulation (e.g. the gate of an NMOS device is at ground) the surface and substrate potentials are nearly the same. In this situation there can be a dramatic increase in avalanche multiplication or band-to-band tunneling when the drain is at a higher potential. Minority carriers underneath the gate are swept to the substrate creating the leakage current.

5. Gate Tunnel Current :- As the oxide thickness scales downwards, the probability of carriers directly tunneling through the gate oxide increases. For oxide thicknesses less than 15 Ä, this gate current can be significant. To reduce the tunnel current, various sandwiches of dielectrics are being explored.