FPGA has 8 million Gates, good memory and clock system. CPLD has 10,000 gates, requires less power and is inexpensive.

Example:

When D = C= y=1;

The output will also be 1. Suppose there will be a delay in the inverter which is greater than the delay of AND gates then output y becomes 0 which is not true from the description of D latch operation. So we can fix this using CPLD.

Here, the problem is CPLD removes AND gate thinking that it is unwanted and gives a D latch again. This problem could be overcome by using another feature available in CPLD. That is providing external input.