What are the Architectural Features of cortex M3 that make it low power device.

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written 6.5 years ago by

hetalgosavi • 1.7k

• modified 6.5 years ago

Cortex M3 processor is designed with various features to allow designers to develop low power applications and products.
It has 2 modes- Sleep mode and deep sleep mode: To reduce Power consumption during idle period.
Cortex CPU has sleep mode i.e it places core into its power mode where it halts execution of instruction with cortex CPU.
A small part of CPU is kept awake so that peripheral interrupts can wake up cortex Core.
The instruction WFI (wait for interrupt) or WFE (wait for event) is executed to place cortex core into sleep mode.
WFI instruction: Core will resume execution and serve pending instruction. It allows low power application to be completely interrupt driven so that core wake up run the code and re-enter into sleep mode.
WFE instruction: It allows the cortex Core to resume execution from the point where it was placed into sleep mode.
WFI & WFE are called using macros.
Low Gate count and design techniques: Reduces circuit activities in processor to allow active power to be decreased.
High Code density: The code is smaller, program size is reduced. Therefore occupies less memory and power consumption is reduced.
Smaller codes result in reduced processing time therefore processor into sleep mode as soon as possible cut down energy use.
Therefore Energy Efficiency of cortex M3 is better than many 8 bit or 16 bit microcontrollers.
Wake up interrupt controller allows processor Core to be powered down, while processor states are retained and when processor is interrupted it can return to active state immediately.
It has a 3 stage pipelining with branched speculation.
32 bit hardware multiplier with 32bit or 64 bit result.
It has around 240 interrupt and NMI that can be prioritized. Interrupt latency reduced to 12 cycles.
It also has a powerful Thumb instruction set.

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