a) PFD/CP Non-linearities

i) Several imperfections in the PFD/CP circuit lead to high ripple on the control voltage even when the loop is locked. Therefore, the ripple modulates the VCO frequency producing a $\omega /f$ that is no longer periodic.

Coincident pulses generated by PFD with zero phase difference.

ii) The PFD implementation in the above figure generates a narrow, coincident pulses on both $Q_A$ and $Q_B$ even when the input phase difference is 0.
-> A and B rises simultaneously, so do $Q_A \,\,and \,\,Q_B$, therefore reset activates.
-> When PLL-locked, $Q_A$ and $Q_B$ turns on the charge pump for a finite period $T_p=10T_D$......($T_D$: Gate delay).

b) Jitter in PLL's

i) $x_1(t): \omega /f$ - contains zero crossing that are evenly spaced in t.

ii) $x_1(t):$ nearly periodic whose period experience small changes deviating the zero crossing from their points.

We say the latter $\omega / f $ suffers from jitters.