i) Speed is the time required for the output voltage to go from zero to the maximum input level after the switch turns on.

ii) Since, $V_{out}$ would take $\infty$ time to became equal to $V_{in_{o}}$, we consider the output settled when it is within a certain "error band", $\Delta V$, around the final value.

iii) The sampling speed is given by 2 factors the on-resistance of the switch and the value of the sampling capacitor.

iv) Thus to achieve higher speed, a large aspect ratio and a small capacitor must be used.

v) ON-resistance depends on the input level, yeilding a greater time constant for more positive inputs.

vi) In order to accomodate a greater voltage swing in a sampling circuit, we first observe that a PMOS switch exhibits an ON-resistance that decreases as input voltage becomes more positive.

vii) For high-speed input signals, it is critical that the NMOS and PMOS switches turn OFF simultaneously so as to avoid ambiguity in the sampled values.