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Let us assume that in figure Vin1 - Vin2 varies from -∞ to ∞ . If Vin1 is much more negative than Vin2, M1 is off, M2 is on, and Id2 = Iss. Thus, Vout1 = Vdd and Vout2 = Vdd - Rd.Iss. As Vin1 is brought closer to Vin2, M1 gradually turns on, drawing a fraction of Iss from Rd1 and hence lowering Vout1. Since, Id1 + Id2 = Iss, the drain current of M2 decreases and Vout2 rises.
As shown in figure (a), for Vin1 = Vin2, we have Vout1 = Vout2 = Vdd - Rd.Iss/2. As Vin1 becomes more positive than Vin2, M1 carries a greater current than M2 does Vout1 drops below Vout2. For sufficiently large Vin1 - Vin2, M1 hogs all of Iss, turning M2 off. As a result, Vout1 = Vdd - Rd.Iss and Vout2 = Vdd. Figure (b) plots Vout1 - Vout2 versus Vin1 - Vin2.
The forgoing analysis reveals two important attributes of the differential pair. First, the maximum and minimum levels at the output are well-defined (Vdd and Vdd - Rd.Iss respectively) and independent of the input CM level. Second, the small signal gain is maximum for Vin1 = Vin2 gradually falling to zero as | Vin1 - Vin2 | increases. In other words, the circuit becomes more nonlinear as the input voltage swing increases. For Vin1 = Vin2, we say the circuit is in equilibrium.
Common Mode Characteristics
(a) Circuit is symmetric but tail current source with finite resistance:
i) As Vin,cm increases, VD increases, thereby increases drain current of M1andM2 and decreases both Vx,Vy.
ii) Due to symmetry, Vx=Vy, so they can be shorted together.
iii) Now, M1,M2 are parallel. Therefore, circuit can be simplified as per fig (c)
iv) −(M1+M2) has twice the width (i.e twice bias current). Therefore twice the transconductance (gm).
∴ CM gain of the circuit will be,
Av,cm=VoutVin,cm
Av,cm=−RD/21/2gm+RSS
Note: In a symmetric circuit, CM variation disturb the bias points, altering the small-signal gain and limiting the output voltage swings.
(b) Effect of mismatches in RD:
i) let, RD1=RD and RD2=RD+ΔRD small mismatch and circuit is symmetrical otherwise
ii) assume M1,M2 identical.
iii) As, Vin,cmincreases,ID1andID2 increases by [gm1+2gmRSS]ΔVin,cm
iv) But, Vx and Vy change by different amount.
ΔVx=−ΔVin,cmgm1+2gmRSS(RD)
ΔVy=−ΔVin,cmgm1+2gmRSS(RD+ΔRD)
[ID=11gm+2RSSVin=gm1+2gmRSSVin]
∴ Change in differential output voltage can be calculated by subtracting ΔVy from ΔVx.
(c) Mismatch in transistor M1 and M2.
Av,cm=Vx−VyVin,cm
Vx=ID1RD=gm1VGSRD
=−gm1(Vin,cm−VP)RD....(1)
Vy=ID2RD
=−gm2(Vin,cm−VP)RD....(2)
Vp=RSS(ID1+ID2)=RSS(gm1VGS1+gm2VGS2)
=RSS(gm1(Vin,cm−VP)+gm2(Vin,cm−VP))
Vp=(gm1+gm2)RSS(gm1+gm2)RSS+1Vin,cm......(3)
Substituting (3) in (1) and (2), we get,
Vx=−gm1(gm1+gm2)RSS+1RDVin,cm
Vy=−gm2(gm1+gm2)RSS+1RDVin,cm
∴Vx−Vy=−(gm1−gm2)(gm1+gm2)RSS+1RDVin,cm
Av,cm=Vx−VyVin,cm=−(gm1−gm2)(gm1+gm2)RSS+1RD