Suppose gate of MOSFET is tied to metal 1 interconnect having a large area (fig.a)
During etching of metal 1, the metal 1 area act as antenna collecting ions and rising in potential.
It is possible that the gate oxide break down(irreversibly) during fabrication.
The antenna effecr may occur for any large piece of conductive material tied to the gate inducing polysilicon itself.
For this reason, submicron CMOS technologies typically reduce the total area of such geometries, thereby minimizing the probability of gate oxide damage.
If large area are inevitable, then a discontinuity can be created as in fig.b
SO that when metal 1 is being etched, the large area is connected to the gate.