In digital electronics, charge sharing is an undesirable signal integrity phenomenon observed most commonly in the Domino logic family of digital circuits. The charge sharing problem occurs when the charge which is stored at the output node in the precharge phase is shared among the output or junction capacitances of transistors which are in the evaluation phase. Charge sharing may degrade the output voltage level or even cause erroneous output value

In the dynamic CMOS circuit technique, clock pulse is given between a PMOS and a NMOS and the NMOS logic is associated between them. The circuit operation is based on first precharging the output node capacitance and subsequently estimating the output level according to the applied inputs. Together these operations are scheduled by a single clock signal which drives one NMOS and one PMOS transistors in each dynamic stage.

When the clock signal is high then precharge transistor p1 turns off and n1 turns on. If the input signal forms a conducting path between the output node and ground then output capacitance will discharge to 0V.When the clock signal is low the PMOS transistor p1 is conducting and the complementary NMOS transistor n1 is off .The output capacitance of the circuit is charged up through the conducting PMOS transistor to a logic high level of VDD.

One simple solution to eliminate charge sharing problem is just to add a weak PMOS pull-up device(with a small W/L ratio) to the dynamic CMOS stage output, which basically forces a high output level except there is a strong pull-down path amongst the output and the ground. It can be observed that the weak PMOS transistor will be turned on only when the precharge node voltage is retained high. Otherwise it will be turned off as output voltage becomes high.