The simplest DRAM cell is the 3T scheme. A 3T DRAM cell has a higher density than a SRAM cell; moreover in a 3T DRAM, there is no constraint on device ratios and the read operation is non destructive.

In this cell, the storage capacitance is the gate capacitance of the readout device, so making this scheme attractive for embedded memory applications; however, a 3T DRAM shows still limited performance and low retention time to severely limit its use in advanced integrated circuits. 3T DRAM utilizes gate of the transistor and a capacitance to store the data value.

When data is to be written, write signal is enabled and the data from the bit line is fed into the cell. When data is to be read from the cell, read line is enabled and data is read through the bit line. 3T DRAM cell occupies less area compared to the 4T DRAM cell.

The 3T1D cell in fig. 5 shows the scheme of the basic cell. The basis of the storage system is the charge placed in node S, written from BL write line when $T_1$ is activated.

Consequently, it has a DRAM cell nature, but it allows a non-destructive read process (a clear advantage over 1T1C memories) and high performance read and writes operation, comparable to 6T.With $T_1$ and $T_3$ transistors as accessing devices, the whole cell is composed by four transistors of similar size to the corresponding of 6T.

This implies a more compact cell structure. In order to write the cell at the BL write line level it is only required to activate $T_1$ through the WL write line. Hence, the S node stores either a 0 or a $V_{DD}-V_{th}$ voltage depending on the logic value.

This voltage results in the accumulation of charge at the gate of devices $D_1$ and $T_2$. A key aspect of the 3T1D memory cell is that the capacitance of the gated diode ($D_1$) when $V_{GS}$ is above $V_{TH}$ is significantly higher with respect to lower voltages, because there is a substantial amount of charge stored in the inversion layer.

In order to read the cell, the read bit line BL read has to be previously pre-charged at $V_{DD}$ level. Then $T_3$ is activated from WL read line. If a high (1) level is stored in S, transistor $T_2$ turns on and discharges the bit line. If a low (0) level is stored in S, transistor $T_2$ does not reach enough conduction level.

The objective of the gated diode $D_1$ is to improve Read Access Time. When a high (1) level is stored in S, $D_1$ connected to WL read line causes a boosting effect of the voltage level in node S. The voltage level reached at node S is close to $V_{DD}$ voltage causing a fast discharge of the parasitic capacitance in BL read. If allow (0) level is stored, transistor $T_2$ keeps turned off.