Subject :- VLSI Design

Topic :- Semiconductor Memories

Difficulty :- Medium

Floor Planning:

• With ever larger designs, it is increasingly important to plan a design at an early stage. This early plan helps constrain later design decisions in terms of area, wire usage, ports, and p y g, port locations. The early stage plan, a.k.a. a floorplan, is fleshed out with increasing details with the design flow.

• The issue is a chicken‐and‐egg problem in that an accurate floorplan is difficult without knowing the details, and yet, building the details is greatly facilitated with a floorplan. So such a plan is a first guess. We use a lot of estimates for area to arrive at a reasonable plan. The plan discussed in this lecture includes area for blocks, ports and their locations routing channels metal layer usage power D.

• Markovic / Slide 2 and their locations, routing channels, metal layer usage, power and ground routing, clock routing, and I/O pins. The result is a diagram of the chip.

This is a plan of the chip,

• Shows the module/blocks
• The space needed for wires
• In a cell it is called the “color plan”;
• Floorplanning tools will help position large blocks, rotating, flipping to minimize the routing between blocks
• Helps predict wiring loads and area of chip
• Floorplan budgets area, wire area/delay.
• Make sure the pieces fit together as planned
• Implement the global layout

Input Required

• Design netlist
• Area requirements
• Power requirements
• Timing constraints
• Physical partitioning information
• Die size vs. performance tradeoff

Optional

• I/O placement
• Macro placement information

Types of Routing

Two levels of of routing

• Global: notional set of abutting channels
• Local: actual geometry required to complete signal connections

Two types of routing Types of Routing

• Channel routing
• Channel may grow in one dimension to accommodate wires
• Pins generally on only two sides
• Switchbox routing
• Cannot grow in any dimension
• Pins are on all four sides, fixing dimensions of the box

Global Routing

• Goal: assign wires to paths through channels
• Don’t worry about exact routing of wires within channel
• Final step is the detailed routing Global Routing and Detailed Routing
• Channel utilization
• Can estimate channel height from global routing using congestion
• Keep all channels about equally full to minimize wasted area

Detailed Routing

• Picking exact route of the wires
• Pay attention to the actual timing constraints
• Route time‐critical signals first
• Shortest path may not be best for global wiring
• May need to rip‐up wires and reroute to improve the global routing