Subject :- VLSI Design

Topic :- Data Path Design

Difficulty :- High

Design procedures in VLSI SoCs are very complex. The designer should consider all possible states and inputs and design the chip in such a way that it works every time in every state and with every possible input. In this article, we discuss metastability, setup time, and hold time when designing a digital VLSI circuit.

Critical Path, Throughput, and Latency

The critical path is the longest path in the circuit and limits the clock speed. When describing a digital circuit there are two other important factors: latency and throughput. Latency is the time needed for an input change to produce an output change; latency can be expressed as a length of time or, in synchronous circuits, as a certain number of clock cycles. Throughput refers to the rate at which data can be processed.

Flip-Flops and Combinational Logic

A digital circuit can consist of sequential logic and combinational logic. Sequential logic refers to circuits whose output depends on previous states. In other words, it involves memory that stores previous states and allows a decision to be made based on these previous states and the current input signals. In the digital realm, flip-flops are the standard devices used for storing previous logic states. In Verilog, we can define a flip-flop by using the reg command:

reg[7:0] states;

The above line defines an 8-bit flip-flop. Flip-flops, which are sensitive to clock transitions rather than clock logic states, are the most basic element of synchronous designs. Combinational logic refers to a circuit that computes an output based only on the current input signals.

Figure 1. sh = ab’+bc.

A simple combinational logic circuit is implemented in Figure 1. Every logic device has a propagation delay. Propagation delay is the time difference between an input change and the corresponding output change. This delay can lead to unexpected behavior, such as when a gate accepts two inputs that come from paths with different numbers of gates (and therefore unequal total propagation delay).

Assume we are in the (1,1,1) input state and the output is steady at 1. If b changes from 1 to zero the output of the lower AND gate will transition before that of the upper AND gate, resulting in a temporary logic low on the output. This logic-low state is invalid, because a (1,0,1) input pattern should produce a logic-high output. This brief invalid output state is referred to as a hazard.

More specifically, this glitch is called a static hazard. Dynamic hazards occur when an input change leads to more than one output glitch. Usually, dynamic hazards occur in complex circuits with multiple gates and logic paths.

In synchronous design, we must ensure that glitches do not result in invalid output states. As mentioned above, for storing previous states designers usually use flip-flops with edge sensitivity. When using flip-flops in digital VLSI designs, we must consider the following:

1. Setup time: the input to a flip-flop should be stable for a certain amount of time (the setup time) before the clock transitions; otherwise, the flip-flop will behave in an unstable manner, referred to as metastability.

2. Hold time: the input of a flip-flop should remain stable for a certain amount of time (the hold time) after the clock transitions.

The following figure provides a visual description of setup time and hold time:

Figure 2. Setup and hold time

Setup Time

A digital circuit designed for FPGA or ASIC purposes needs combinational logic for calculations. We usually build multipliers, subtractors, adders, etc., with logic gates. For storing input and output values for these combinational logic circuits, we use flip-flops. Flip-flops are at the beginning and at the end of all critical paths, as shown in Figure 3.

To avoid a setup-time violation when using flip-flops at the end of a combinational path, the output must be stable before the clock edge. Thus, the total propagation delay of a combinational path must not cause the output to transition such that the relationship between the clock signal and the data signal leads to a setup-time violation.