Subject :- VLSI Design

Topic :- Data Path Design

Difficulty :- High

$C^2MOS\,\, Logic \,\,Style $

The logic is implemented in both n- and p- transistors in the form of a pull up p- block and a complementary n-block pull down structure. However the logic in this case is evaluated only during the on period of the clock

Clocked CMOS circuits with gradually rising and falling power-clock are expected to obtain a significant energy saving.

Based on the basic clocked CMOS inverter shown in Fig.2(a), we can realize NOR, NAND functions by using switches in series and parallel, then the clocked CMOS circuits with more complicated logic function may be achieved.

Clocked CMOS flip-flop
In the previous section we found that the signal at each node is fixedly set to base-0 or base-1 when clk = 0 . In this way, a signal never be stored in this period. Thus, we cannot build a flip-flop by simply using gates as usual.

Clocked CMOS circuits, which adopt gradually rising and falling power-clock, can result in a considerable energy saving. However, the demand that the output signal should track the power-clock’s gradually rising and falling behavior during charging and discharging makes the circuit design even difficult.

At present, the existing researches either adopt retractile cascade power clocks or use multiple phase power clocks with memory schemes in the design. The problem is: the applicability of the designed clocked circuits is awfully limited.

We think that the research on algebra expression of clocked signals and the design of basic clocked gates are two key researches. Therefore, this paper firstly presents a systematic study of clocked signals using an appropriate algebra expressions, and fully exploits the four types of clocked signal.

Furthermore, some clocked CMOS gate circuit based on transmission gate are proposed. The clocked transmission gate supplied with a trapezoidal power clock was simulated with PSPICE and demonstrated to have correct logic function and considerable energy saving.

The design principle can also be extended to design more complicated clocked CMOS circuits. If the clocked CMOS flip-flops are compounded, the design of low power clocked CMOS sequential circuits can be realized.