SR Flip Flop

• The SR flip flop stands for "Set-Reset" flip flop.
• It is the clocked and simplest type of flip flops.
• The SET input 'S' sets the device or produces output 1.
• The RESET input 'R' reset the device or produce the output 0.
• The reset input is used to get back the flip flop to its original state from the current state with an output 'Q'.
• This output depends on the set and reset conditions, which is either at the logic level "0" or "1".

Logic Symbol for SR Flip Flop:

The logic symbol for SR Flip Flop is as shown below-

• Two methods are used to construct SR flip flop are as follows:
  • By using NOR Latch
  • By using NAND Latch

Construction of SR Flip Flop By Using NOR Latch:

• Construction of SR using this method requires NOR latch and Two AND gates.

Construction of SR Flip Flop By Using NAND Latch:

• Construction of SR using this method requires NAND latch and Two NAND gates.

Truth Table for SR Flip Flop:

This truth table further simplifies as follows:

K - Map for SR Flip Flop:

• By using the above Truth Table K-Map can be drawn for SR flip flop as follows:

From the above k-map Characteristic Equation of SR Flip Flop can be calculated as follows:

$$Q_{n+1} = (SR + SR’) (Q_n + Q_n') + Q_n (S’R’ + SR’)$$

$$= S.(R + R') (Q_n + Q_n') + Q_n R' (S' + S)$$

$$= S.1.1 + Q_n.R'.1$$

$$= S + Q_n.R '$$

$$Q_{n+1} = S + Q_n.R'$$

Excitation Table for SR Flip Flop:

The excitation table tells the inputs required. for the given combination of present state Q_n and next state Q_n+1, excitation table tell the inputs required.